View P9025AC_9043971.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

datasheet P9025AC 09/01/15 1 ?2015 integrated device technology, inc. 5w, qi wireless power receiver with integrated rectifier and ldo output P9025AC features ? integrated single chip receiver (rx) solution ? integrated full-bridge synchronous rectifier ? integrated 5.3v, 1a ldo regulator output ? wpc-1.1.2 compliant ? advanced wpc v1.1 .2 foreign object detection (fod) ? programmable fod setting via external resistor ? closed-loop power transfer control between tx and rx ? support i 2 c interface with access to: ? rectifier voltage ? output current ? resonance frequency ? open-drain led indicator output ? over-temperature/voltage/current protection ? 0 to +85c temperature range ? 5 x 5 mm 32-vfqfpn package applications ? pc peripherals ? rugged electronic gear ? small appliances ? battery-powered electronics introduction the P9025AC is an integrated single-chip, wpc-1.1.2 compliant wireless power receiv er with an advanced foreign object detection (fod) feature. this device operates with an ac power signal from a resonant tank and converts it into a regulated 5.3v output voltage. the receiver includes a high efficiency synchronous full bridge rectifier and 5.3v tracking ldo output stage. the P9025AC automatically detects the transmitter?s presence and initiates wpc ac modulation communication protocols with optimal efficiency. the device includes the control circuit required to modulate the load to transmit wpc-compliant message packets to the base station. it uses minimal external components to reduce overall solution area and costs. the P9025AC employs advanced programmable wpc fod techniques to detect foreign metallic objects placed on the transmitter base station derived from a transmitted and received power transfer algorithm. typical application circuit P9025AC ac1 vrect c rect stat r 1 agnd ac2 scl sda scl sda c s c d en out c out v out =5.3v enable acm1 acm2 c mod1 c mod2 c clamp2 c clamp1 c bst1 c bst2 clamp2 bst2 bst1 clamp1 pgnd ilim r lim teop charge ? complete int l rx fod1 r fod1 c 1 vdd fod2 r fod2 interupt temperature ? sense chg_end ? / ? cs100 sns
5w, qi wireless power receiver with inte grated rectifier and ldo output 2 09/01/15 P9025AC datasheet absolute maximum ratings stresses above the ratings listed below ( ta b l e 1 and ta b l e 2 ) can cause permanent damage to the P9025AC. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional op eration of the device at thes e or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to abs olute maximum rating conditions for ex tended periods can affect product reliability. electrical paramete rs are guaranteed only over t he recommended operating temperature range. table 1: absolute maximum ratings summary table 2: package thermal information 1,2,3,4 notes: 1. the maximum power dissipation is p d(max) = (t j(max ) - t a ) / ja where t j(max) is 125c. exceeding the maximum allowable power dissipation will result in excessive die temperature, and the device will enter thermal shutdown. 2. this thermal rating was calculated on jedec 51 standard 4-la yer board with dimensions 3" x 4.5" in still air conditions. 3. actual thermal resistance is affected by pcb size, solder joint quality, layer count, copper thickness, air flow, altitude, and other unlisted variables. 4. for the nbg32 package, connecting the 5 mm x 5 mm ep to intern al/external ground planes with a 5x5 matrix of pcb plated-thro ugh-hole (pth) vias, from top to bottom sides of the pcb, is recommended for improving the overall thermal performance. table 3: esd information pins rating units ac1, ac2, vrect, acm1, acm2, clam p1, clamp2 to pgnd_ -0.3 to 20 v bst1, bst2 to pgnd1 -0.3 to (ac1, ac2 + 6) v int , en , stat , scl, sda, out, sns, teop, rlim, chg_end/ cs100, fod1, fod2, vdd to agnd -0.3 to 6 v pgnd, pgnd1, pgnd2, to agnd -0.3 to 0.3 v out current 1.5 a ac1, ac2 current 2a rms symbol description rating (vfqfpn) units ja thermal resistance junction to ambient 35 ? c/w jc thermal resistance j unction to case 29.6 ? c/w jb thermal resistance junction to board 2.4 ? c/w t j operating junction temperature 0 to +125 ? c t a ambient operating temperature 0 to +85 ? c t stg storage temperature -55 to +150 ? c t lead lead temperature (soldering, 10s) 300 ? c test model pins ratings units hbm all pins 1500 v cdm all pins 500 v
09/01/15 3 5w, qi wireless power receiver wi th integrated rectifier and ldo output P9025AC datasheet electrical specifications table table 4: device characteristics v rect = 6v, c out = 1f, c vrect = 20f, v en = gnd, t a = 0 to +85c, unless otherwise noted. typical values are at 25c. symbol description co nditions min typ max units v rect under-voltage lock-out v uvlo under-voltage lockout rising voltage on v rect 2.3 2.5 2.7 v v uvlo-hys uvlo hysteresis 50 mv v rect over-voltage protection v ovp over-voltage v rect rising voltage on v rect 13.3 v v ovp-hys over-voltage hysteresis 1.5 v power supply current i rect quiescent current i out = 0ma, with internal load 14 16 18 ma i out = 0ma, no internal load 2 3 4 ma low-drop-out regulator i lim output current limit r lim = 30k ? 1.15 1.6 1.95 a r lim < 25k ? 1 2.0 v out regulated output voltage i out = 0ma to 1000ma 5.04 5.3 5.56 v v dd voltage (for internal supply use only) v dd_int internal supply voltage i vdd = 100 ? a, maximum allowable load for test purposes 4.44 4.54 4.64 v thermal shutdown t shd thermal shutdown threshold temperature rising 150 c temperature falling 130 c digital input and output characteristics v il logic level input low en , teop 0.4 v v ih logic level input high en , teop 1.3 v v ol open drain; stat , int i stat = 4ma 400 mv r pd pull-down resistance en 200 k ? teop 1000 switch on-resistance r dson acm1, acm2 switches 150ma 2500 m ? clamp1, clamp2 switches 600 m ? rectifier bridge switches 250 m ? scl, sda (i 2 c interface) f scl clock frequency 0 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t hd,sta hold time (repeated) for start condition 0.6 s
5w, qi wireless power receiver with inte grated rectifier and ldo output 4 09/01/15 P9025AC datasheet notes: 1. guaranteed by design and not subject to 100% production testing. 2. guaranteed by design and simulation. t su:sta set-up time for repeated start condition 0.6 s t su:dat data setup time 100 ns t hd:dat data hold time 0.9 s t su:sto setup time for stop 0.6 s t buf bus free time between stop & start 1.3 s t r rise time of both sda and scl signals (note 1,2) 20 + 0.1 c b 300 ns t f fall time of both sda and scl signals 1,2 20 + 0.1 c b 300 ns t sp spike pulse widths suppressed by input filter 1,2 050ns c b capacitive load for each bus line 1,2 400 pf c bin scl, sda input capacitance 1,2 60 pf v il input threshold low 0.4 v v ih input threshold high 1.4 v i i input leakage current -1.0 1.0 a symbol description co nditions min typ max units
09/01/15 5 5w, qi wireless power receiver wi th integrated rectifier and ldo output P9025AC datasheet typical performance characteristics figure 1. system efficiency vs. load current v in = 5v, v out = 5.3v, spacer = 3.7mm, cs = 247nf, t a = 25c measured using the P9025AC-r-evk v1.0 (receiver) and p9038-r-evk v1.0 (transmitter) reference boards. figure 2. load regulation vs. load current v in = 5v, v out = 5.3v, spacer = 3.7mm, cs = 247nf, t a = 25c measured using the P9025AC-r-evk v1.0 (receiver) and p9038-r-evk v1.0 (transmitter) reference boards.
5w, qi wireless power receiver with inte grated rectifier and ldo output 6 09/01/15 P9025AC datasheet pin configuration pin descriptions pin # name type function 1int o interrupt output. open drain output pin. a low st ate indicates that an over-current, over-voltage, or over-temperature condition has oc curred. if used, connect a 100k ? pullup resistor to the out pin or compatible system i/o voltage rail. 2 dnc1 dnc do not connect. it is internally co nnected. this pin must be left floating. 3 dnc2 dnc do not connect. it is internally co nnected. this pin must be left floating. 4 bst2 o bootstrap output for high-side rectifier fet 2. connect a 0.01f capacitor from ac2 pin to bst2. 5 bst1 o bootstrap output for high-side rectifier fet 1. connect a 0.01f capacitor from ac1 pin to bst1. 6 ac1 i ac1 input to the inte rnal full-wave rectifier. 7 vrect o output of the full-wave rectifier. bypass this pin with ceramic capacitors to power ground. 8 rlim i current-limit resistor. a resist or connected between this pin and ground sets the current limit of the 5v ldo output. 9 sns i ldo output sense pin. connect to the out pin. 10 chg_end / cs100 i active-high input pin. default settin g is a charge-end active-high input from an external battery charger to terminate power transfer. alternativel y, a charge-status active high input which will send a wpc charge status packet with value 100 (100% charge). this pin has an internal pull down resistor. 1 2 3 4 5 6 7 11 12 13 14 15 16 30 29 28 27 26 25 8 23 22 21 20 19 18 17 24 int dnc1 dnc2 bst2 bst1 ac1 vrect rlim nc4 acm2 pgnd1 acm1 fod2 clamp1 pgnd2 clamp2 ac2 vdd agnd scl sda fod1 nc1 out nc2 en teop nc3 32 31 stat pgnd 9 10 sns chg_end / cs100 ep
09/01/15 7 5w, qi wireless power receiver wi th integrated rectifier and ldo output P9025AC datasheet 11 nc1 nc not internally connected. this pin may be conne cted to others to facilitate routing or to improve thermal performance. 12 out o regulated 5.3v output voltage. connect a 1 f in parallel with 4.7 f capacitor between the pin and ground. 13 nc2 nc not internally connected. this pin may be conn ected to others to facilit ate routing or to improve thermal performance. 14 en i active-low enable pin. the chip is suspended and plac ed in low-current (sleep) mode when this pin is pulled high. this pin has internal pu lldown resistor to analog ground (agnd). 15 teop i active-high over-temperature in put pin. when pulled high, the ch ip will disable the ldo output and send a wpc end-of-power packet with code 0x 03 (over-temperature code). this pin has an internal pull down resistor to ground. 16 nc3 nc not internally connected. this pin may be conne cted to others to facilitate routing or to improve thermal performance. 17 clamp2 i ac clamp input 2. connect a 0.47uf capacitor from this pin to ac2 pin. 18 pgnd2 - power ground for the ac clamp fets. 19 clamp1 i ac clamp input 1. connect a 0.47uf capacitor from this pin to ac1 pin. 20 fod2 i fod2 adjustment. a resistor between this pin and agnd sets t he fod offset value used in the internal fod calculation. 21 acm1 i ac modulation input 1. connect a 22nf capacitor from this pin to ac1 pin. 22 pgnd1 - power ground for the full-wave rectifier. 23 acm2 i ac modulation input 2. connect a 22nf capacitor from this pin to ac2 pin. 24 nc4 nc not internally connected. this pin may be conne cted to others to facilitate routing or to improve thermal performance. 25 fod1 i a resistor between this pin and analog groun d selects the fod compensation curve that is used for the internal fod calculation. 26 sda i/o i 2 c data port. connect a 2.2k pullup resistor from this pin to ou t (pin) voltage or the system io voltage rail. if not used, connect to ground. 27 scl i i 2 c clock port. connect a 2.2k pullup resistor from this pin to out voltage or the system io voltage rail. if not used, connect to ground. 28 agnd - analog ground connection. 29 vdd o internal voltage supply. connect a 1uf capacitor between this pin and analog ground. do not connect any external load to this pin. 30 ac2 i ac2 input to the inte rnal full-wave rectifier. 31 pgnd - power ground for the full-wave rectifier. 32 stat o status output. a logic low state indicates that power is being transferred. pin # name type function
5w, qi wireless power receiver with inte grated rectifier and ldo output 8 09/01/15 P9025AC datasheet block diagram pgnd driver & control peripherals stat i c scl sda gnd otp + digital multi channel adc with analog mux and digital control out vrect ldo5v control ac1 ac2 acm1 acm2 clamp1 clamp2 bst1 bst2 ac modulation and overvoltage protection gnd en internal ldo gnd 4.5v rlim current limit control ntc reading ts 2 sns (qfn only) chg_end / cs100 fod1 fod2 vdd vin-uvlo
09/01/15 9 5w, qi wireless power receiver wi th integrated rectifier and ldo output P9025AC datasheet description of the wireless power charging system a wireless power charging system has a base station with one or more transmitters that ma ke power available via dc-to-ac inverter(s) and transmit the power over a strongly-coupled inductor pair to a receiver in a mobile device. the transmitter may be a free-positioning or magnetically-guided type. a free-positioning type of transmitter has one coil or an array of coils that offers limited spatial freedom to the end-user, whereas a magnetically-guided type of transmitter helps the end-user align the receiver to the transmitter with a magnetic attraction. the amount of power transferred to the mobile device is controlled by the receiver. the receiver sends communication packets to the transmitter to in crease power, de crease power, maintain the power level, or terminate power transfer. the bit rate for rx-to-tx communication link is 2kbps. the communication is digital and communication of 1's and 0's is achieved by the rx modulating the amount of load on the receiver coil. to conserve power, the transmitter places itself in a very-low-power sleep mode unless it detects the presence of a receiver. once a receiver is detected, the transmitter exits sleep mode and begins the power transfer per the wpc specification. theory of operation the P9025AC is a highly-integrated wpc (wireless power consortium)-compliant wireless power receiver ic for mobile devices. it can transfer 5w of power from a wireless transmitter to a load (ex. a battery charger) in wpc "qi" mode using near-field magnetic induct ion. for complete details of the wpc wireless power syst ems, refer to the wpc specifications and other materials at http://www.wirelesspowerconsortium.com . overview the simplified internal block diagram of the P9025AC is shown on page 8 . an external inductor and capacitor transfers energy from the transmitter's coil through the P9025AC's ac1 and ac2 pins to be full-wave-rectified and stored on a capacitor connected to v rect. until the voltage across the capacitor exceeds the threshold of the vin_uvlo block, the rectification is performed by the body diodes of the synchronous full bridge rectifier fets. after the internal biasing circuit is enabled, the driver and control block operates the mosfet switches in the rectifier synchronously with the applied ac signal for increased efficiency. an internal adc monitors the voltage at v rect and the load current. using this information, the P9025AC sends instructions to the wireless power transmit ter to increa se, maintain, or decrease the amount of power transferred. the P9025AC may also instruct the transmitter to terminate power transmission based on various conditions and other inputs. power control the voltage at v rect and the current through the rectifier are sampled periodically and digitized by the adc. the digital equivalents of the voltage and current are supplied to the internal control logic, which decides whether the loading conditions on v rect indicate that a change in the operating point is required. if the load is heavy enough to bring the voltage at v rect below its target, the tr ansmitter is instructed to move its frequency lower, closer to resonance. if the voltage at v rect is higher than its target, the transmitter is instructed to increase its frequency. to ma ximize efficiency, the voltage at v rect is programmed to decrease and become closer to the ldo output voltage as the ldo's load current increases. when the load current is small, a higher v rect is desirable so that the system can better handle a sudden load increase. wpc characteristics startup and power transfer when a mobile device containing the P9025AC is placed on a wpc "qi" charging pad, it responds to the transmitter's "ping" signal by rectifying the ac power from the transmitter and storing it on a capacitor connected to v rect. during the "ping" phase, the rectifier provides about 5v at the v rect pin. an internal linear voltage regulator provides the supply voltage for the digital section to enable wpc communication. to increase the reliability of the communicati on, an internal load of about 15ma is connected to v rect until the external load is large enough to support communication. the P9025AC then communicates its identification and configuration information to the transmitter. after this, the system is in the power transfer state. the control loop of the P9025AC then adjusts the rectifier voltage to 7v by sending control error packets instructio n to the transmitter. the ldo output is enabled and power is delivered to the load after v rect initially reaches 7v. during power delivery to the load, the P9025AC control circuit continues to send control error packets to the transmitter to adjust the rectifier voltage to the level required to maximize the efficiency of the linear regulator.
5w, qi wireless power receiver with inte grated rectifier and ldo output 10 09/01/15 P9025AC datasheet advanced foreign object detection (fod) when metallic objects are exposed to an alternating magnetic field, eddy currents cause such objects to heat up. examples of parasitic metal objects as such are coins, keys, paper clips, etc. the amount of heating depends on the strength of coupled magnetic field, as well as on the characteristics of the object, such as its resistivity, size, and shape. in a wireless power transfer system, the heating manifests itself as a power loss, and therefore a reduced power transfer efficiency. moreover, if no appropriate meas ures are taken, the heating could be sufficient that the foreign objects may become heated to an undesirable temperature. during power transfer state, the receiver periodically will communicate to the transmitter the amount of power received by means of a received powe r packet. the transmitter will compare this power with the amount of power transmitted during the same time period. if there is a significant unexplained loss of power, then the transmitter will shut off power delivery, because a possible foreign object may be absorbing too much energy. for a wpc system to perform this function with sufficient accuracy, both the transmitter and receiver need each to account for and compensate fo r all of their known losses. such losses could be to resistive losses, nearby metals that are part of the transmitter or re ceiver, etc. because the system accurately measures its power and accounts for all known losses, it can thereby detect foreign objects owing to their creation of an unknown loss. the P9025AC employs advanced fod techniques to both accurately measure its received power, and to accurately compensate all of its known losses. this compensation is implemented by means of a curv e fitting table. this table supports up to 10 different curves stored in otp (one time programmable) memory. the 10 programmed otp settings are externally selected by means of the fod1 selection resistor value (see page 14 ) which selects the settings that best match a particular system characteristic. additionally, the i 2 c interface supports 1 volat ile fod compensation setting that can be selected that will override the otp memory settings. a further enhancement is selected by the fod2 offset resistor which adds a -3 00 to +300mw power offset to the values selected by the fod1 resistor. this is useful to tune the selected compensation curve up or down to optimally match the actual known receiver system losses. for more information about how to determine and program the fod settings, refer to application note an-886 P9025AC fod tuning guide . over-voltage protection in the event that the input voltage increases above 15v, the control loop disables the ldo, and sends error packets to the transmitter in an attempt to bring the rectifier voltage below 7v. if the voltage at v rect exceeds vovp, two internal fets turn on to clamp the ac inputs to quickly reduce the v rect voltage. this is accomplished through loading the receiver resonant tank with extra capacitance shorted to ground through the above mentioned internal fets. this changes the parallel resonance of the tank circuit wh ich causes the tx to rx gain to decrease dramatically. the clamp is released when the v rect voltage falls below the vovp hysteresis level. v rect must not be directly loaded. over-current protection and thermal shutdown the P9025AC employs over-cur rent and thermal protection by sending an end of power packet to the transmitter when the output current reaches the current limit level or the die temperature exceeds the thermal shutdown level. the ldo output is also disabled during these conditions. the current limit level is programmable with an external resistor: for any value of rlim below 25k ? , the output current is limited to 2-amps. however, rl im is not recommended to be set higher than 60 k ?? rectifier and v rect level once v rect powers up to greater than 7v, the full-bridge rectifier switches to half sy nchronous or full synchronous mode (depending on the loading conditions) to efficiently transfer energy from the transmitter to v rect. the control loop of the P9025AC maintains the re ctifier voltage between 5.45v and 7v, depending upon the output current (i out ). the rlim resistor sets both the current limit (i lim ) and the v rect steps based on i set which is a reference cu rrent used to partition the i out load range into 4 regions, each with a v rect target for efficiency and transient optimization. i set is equal to: the recommended value of r lim for a 1a output is 30 k ? . i lim 45000 r lim -------------- - = i set 38000 r lim -------------- - =
09/01/15 11 5w, qi wireless power receiver wi th integrated rectifier and ldo output P9025AC datasheet table 5: v rect target range status output the stat output goes low when the ldo output is enabled. interrupt output the int output goes low to indicate that an over-current, over-voltage or over-temperature event has occurred. see the electrical specifications for threshold levels. enable input if the particular application requires the P9025AC to be disabled, this can be accomplished with the en pin. when the en pin is pulled high, the device is suspended and placed in low current (sleep) mode. if the en pin is pulled low or floating, the device is active. teop input the P9025AC can optionally be shut down with the teop pin. this pin is typically used to shut down the P9025AC if the battery charger or host system determines an over-limit high temperature condition. when the teop pin is pulled high, the P9025AC will disable its ldo ou tput, and also send an end-of-power packet to the transmitter with code 0x03 (over-temperature code). in response to the end-of-power packet, the transmitter will immedi ately stop power transfer and go into a sleeping (no power offered) condition for some period of time. the amount of sl eep time is not prescribed by wpc and varies among different transmitters. a common value used for this over-temperature sleep time is approximately 5-minutes. chg_end / cs100 this pin has two functions. the charge-end default function can be used to terminate power transfer with the transmitter. when chg_end is pulled high, the P9025AC will send a wpc end-of-charge packet with a code value of 0x01 (charge complete code). in resp onse to this, the transmitter should immediately stop power transfer and go into a sleeping (no power offered) condition for some period of time. the amount of sleep time is not prescribed by wpc and varies from 5-seconds to much longer, depending on the transmitter design. if the pin is set in charge-s tatus mode, the device will send a wpc charge status packet with value 100 (100% charge) indicating a fully charged bat tery . ldo the primary output of the P9025AC device is a linear regulator that receives its input from v rect. the ldo supplies power to the system and/or charging circuitry. the output provides a nominal 5.3v with 1 a output curr ent capability. the voltage is intentionally set 0.3v higher than the standard 5v rail to provide extra headroom for voltage drops that may be encountered in the system under heavy loads. modulation/communication receiver-to-transmitter communi cation is accomplished by modulating the load seen by the receiver's inductor. to the transmitter, this appears as an impedance change, which results in measurable variations of the transmitter's output waveform. modulation is done with ac modulation, using internal switches to connect external capacitors from ac1 and ac2 to ground. the communication protocol is covered in the next section. wpc communication the P9025AC communicates with the base via communication packets. each communication packet has the following structure: figure 3. communication packet structure in accordance with the wpc specification, the power receiver communicates with the power transmitter using load modulation. the load seen by the power transmitter's inductor is modulated on the receiver side in a periodic fashion to send packets. the power transmitter detects this as a modulation of coil current/voltage to receive the packet information. v rect i out 7v i out < 10% of i set 6.3v 10% of i set < i out < 20% of i set 5.5v 20% of i set < i out < 40% of i set 5.45v 40% of i set < i out
5w, qi wireless power receiver with inte grated rectifier and ldo output 12 09/01/15 P9025AC datasheet bit encoding scheme as required by the wpc, the P9025AC uses a differential bi-phase encoding scheme to modulate data bits onto the power signal. a clock frequency of 2khz is used for this purpose. a logic one bit is encoded by generating two transitions per clock period, whereas a logic zero bit is encoded using only one transition per clock period as shown below: figure 4. bit encoding scheme each byte in the communication packet comprises 11bits in an asynchronous serial format, as shown below: figure 5. byte encoding scheme each byte has a start bit, 8 data bits, a parity bit, and a single stop bit. system feedback control the P9025AC is fully compatible with wpc specification rev. 1.1.2 and has all necessary circuitry to communicate with the base station via wpc-compliant communication packets. the overall wpc-compliant system behavior between the transmitter and receiver follows the state machine below: figure 6. wpc system feedback control the P9025AC goes through four phases: start/selection, ping, identification & configuration, and power transfer. start/selection in this phase, the P9025AC senses the incoming power from the base station transmitter and pr oceeds to the ping state. it monitors the rectified voltage, and when the voltage is above the v rect, uvlo threshold, the P9025AC wakes up its digital electronics and prepares to communicate with the base station. if the P9025AC does no t proceed to ping, then it does not transmit any communication packets. ping in this phase, the P9025AC transmits a signal strength packet as the first communication packet to instruct the base to keep the power signal on. after sending the signal strength packet, the P9025AC proceeds to the identification and configuration phase. if, inst ead, the P9025AC sends end of power packets, then it remains in the ping phase. in this phase, the P9025AC sends the following packets: ? signal strength packet ? end of power packet identification and configuration (id & config) in this phase, the P9025AC may send the following packets: ? identification packet ? configuration packet after sending the configuration packet, the P9025AC proceeds to the power transfer phase. power transfer in this phase, the P9025AC controls the power transfer from the power transmitter by means of the following control data packets: ? control error packets ? rectified power packet ? end power transfer packet modulation the P9025AC is compatible with wpc v1.1.2 transmitter coils. each receiver coil type has a unique inductance value and various physical properties as are best for a given application. as such, the resonant capacitor (cs) that is used with a given receiver coil should be optimized for the overall application. the wpc guidance for cs is that the resonant frequency of the receiver coil and cs capacitor should be 100khz while placed on the surface of a transmitter with the normal spacing. t clk one zero one zero one one zero zero start stop parity b 012 34 56 7 b bbbbb b
09/01/15 13 5w, qi wireless power receiver wi th integrated rectifier and ldo output P9025AC datasheet application information external components the P9025AC requires a minimum number of external components for proper operation, as indicated in the reference schematic. ldo input capacitor (v rect capacitors) the ldo input capacitors (v rect capacitors) should be located as close as possible to the v rect pins, and ground (pgnd). ceramic capacitors are recommended for their lower esr and small profile. v dd capacitor the P9025AC has an internal ldo regulator that must be bypassed with a 1f capacitor connected from the v dd pin to gnd. this capacitor should be as close as possible to the v dd pin with a close gnd connection. output capacitor a 0.1f and a 4.7f capacitors in parallel must be connected from this pin to ground (pgnd). the trace should be made as short as practical for maximum device performance. since the ldo has been designed to function with very low esr capacitors, a ceramic capaci tor is recommended for best performance. for better transient response increase the total amount of output capacitance. for 1-amp load steps, an output capacitance of at least 10f is recommended. nc and dnc pins nc pins that are indicated as ?not internally connected? should be soldered to the pcb ground plane to improve thermal performance with multiple vias exiting the bottom side of the pcb. this improves heat flow away from the package and minimizes package thermal gradients. dnc pins that are indicated as ?internally connected? must be left floating. pcb layout considerations for optimum device performance and lowest output phase noise, idt recommends that cu stomers copy the reference layout used in the P9025AC -r-evk referenc e kit. more information and layout files can be found at http://www.idt.c om/P9025AC-r-evk. additional layout guidelines can be found in application note an-889 P9025AC layout guidelines . users are encouraged to read this document prior to starting a board design. power dissipation and thermal requirements the P9025AC is offered in a vfqfpn-32 package which has a maximum power dissipation ca pability of about 1.9w. the maximum power dissipation is det ermined by the number of thermal vias between the pack age and the printed circuit board, combined with the ability of the board to ultimately transfer the thermal energy into the ambient environment. the maximum power dissipation is def ined by the dies specified maximum operating junction temperature, t j , of 125c. the junction temperature rises when the heat generated by the device's power dissipation goes through the package thermal resistance. the vfqf pn package offers a typical thermal resistance, junction to ambient ( ja ), of 35c/w when the pcb layout and surrounding devices are optimized as described in application note an-889 P9025AC layout guidelines . thermal overload protection the P9025AC integrates thermal overload shutdown circuitry to prevent damage resulting from excessive thermal stress that may be encountered under fa ult conditions. this circuitry will shut down and reset the de vice if the die temperature exceeds 150c. to allow the maximum load current on each regulator and the synchronous rectifier, and to prevent thermal overload, it is important to ensure that the heat generated by the P9025AC is dissipated efficiently into the pcb and environment end of charge (eoc) in the event of thermal shutdown (150c), en, chg_end or teop pins assertion the device turns off the ldo and continually sends end of po wer (eop) packets until the transmitter removes the power and the rectifier voltage on the receiver side drops below the uvlo threshold. special notes 32-vfqfpn package assembly note 1 : unopened dry packaged parts have a one year shelf life. note 2 : the hic indicator card for newly-opened dry packaged parts should be checked. if there is any moisture content, the parts must be baked for a minimum of 8 hours at 125c within 24 hours of the assembly reflow process.
5w, qi wireless power receiver with inte grated rectifier and ldo output 14 09/01/15 P9025AC datasheet reference schematic (P9025AC-r-evk v1.0) the reference schematic b ill-of-materials can be fo und in the P9025AC-r-evk reference board manual. 5 5 4 4 3 3 2 2 1 1 d d c c b b a a P9025AC-r-evk v1.0 2. i2c pins must not float (pull-up or pull-down). 1.fod1 (r4) is for selecting internal otp settings and fod2 (r5) is for adding offset to the fod1 setting. values will be determined during pre-production. 3. connections for programming fod settings and reading i2c: vrect, /en, sda, scl, gnd. notes: rx coil connections 4. teop and chg_end/cs100 inputs may be directly connected to gnd if these functions are not required. this document contains information proprietary to integrated device technology, inc. (idt). use or disclosure without the written permission of an officer of idt is expressly forbidden optional clamp2 acm2 acm1 /en ac1 ac2 bst1 stat sda bst2 ac1 clamp1 bst1 clamp2 bst2 ac2 vrect clamp1 scl rlim out lc_node 0 0 0 0 0 0 0 0 0 bst1 clamp1 bst2 clamp2 acm2 acm1 acm1 acm2 bst1 bst2 clamp1 clamp2 vrect title size document number r e v date: sheet of 305-pd-15-0285 1 P9025AC-r-evk v1.0 custom 22 tuesday, august 04, 2015 title size document number r e v date: sheet of 305-pd-15-0285 1 P9025AC-r-evk v1.0 custom 22 tuesday, august 04, 2015 title size document number r e v date: sheet of 305-pd-15-0285 1 P9025AC-r-evk v1.0 custom 22 tuesday, august 04, 2015 c2 22nf 50v r3 0 c7 1uf int 28awg c13 4.7uf u1 P9025AC qfn /en 14 bst1 5 bst2 4 scl 27 sda 26 fod1 25 rlim 8 fod2 20 chg_end/cs100 10 teop 15 agnd 28 pgnd1 22 pgnd2 18 /int 1 dnc1 2 dnc2 3 /stat 32 clamp2 17 acm2 23 acm1 21 sns 9 vdd 29 vrect 7 pgnd 31 ac1 6 out 12 clamp1 19 nc1 11 ac2 30 epad 33 nc2 13 nc3 16 nc4 24 r5 47k c4 47nf 50v out 28awg chg_end 28awg c15 4.7uf c16 4.7uf r1 4.7k c10 10nf 50v c18 4.7uf c8 10nf 50v stat 28awg c6 0.1uf 50v c3 1.8nf 50v /en 28awg r2 4.7k d3 green c12 0.47uf 50v sda c14 4.7uf c11 0.1uf r7 4.7k r4 np vrect 28awg i2crail 28awg gnd 28awg scl c17 1uf teop 28awg r6 30k c9 22nf 50v c5 0.1uf 50v c1 0.47uf 50v l1 inductor gnd1 28awg
09/01/15 15 5w, qi wireless power receiver wi th integrated rectifier and ldo output P9025AC datasheet i 2 c register map the P9025AC has a one-time programmable i 2 c address that is set to default 0x25h. table 6: read registers ? v rect voltage: v rect = 5 x adc1<12:1> = [adc1<12:1>] x 5 x [1.8v/2 12 ] table 7: read registers ? i out current: i out is read directly from i out = adc2<12:1> = [adc1<12:1>] x [1.8a/2 12 ] byte address byte name bit field field name type default value description 0x40 reg0 7 adc1<12> r v rect adc code (average of 8 consecutive measurements) 0x40 reg0 6 adc1<11> r v rect adc code (average of 8 consecutive measurements) 0x40 reg0 5 adc1<10> r v rect adc code (average of 8 consecutive measurements) 0x40 reg0 4 adc1<9> r v rect adc code (average of 8 consecutive measurements) 0x40 reg0 3 adc1<8> r v rect adc code (average of 8 consecutive measurements) 0x40 reg0 2 adc1<7> r v rect adc code (average of 8 consecutive measurements) 0x40 reg0 1 adc1<6> r v rect adc code (average of 8 consecutive measurements) 0x40 reg0 0 adc1<5> r v rect adc code (average of 8 consecutive measurements) 0x41 reg1 7 adc1<4> r v rect adc code (average of 8 consecutive measurements) 0x41 reg1 6 adc1<3> r v rect adc code (average of 8 consecutive measurements) 0x41 reg1 5 adc1<2> r v rect adc code (average of 8 consecutive measurements) 0x41 reg1 4 adc1<1> r v rect adc code (average of 8 consecutive measurements) 0x41 reg1 3 reserved r reserved 0x41 reg1 2 reserved r reserved 0x41 reg1 1 reserved r reserved 0x41 reg1 0 reserved r reserved byte address byte name bit field field name type default value description 0x42 reg2 7 adc2<12> r i out adc code (average of 8 consecutive measurements) 0x42 reg2 6 adc2<11> r i out adc code (average of 8 consecutive measurements) 0x42 reg2 5 adc2<10> r i out adc code (average of 8 consecutive measurements) 0x42 reg2 4 adc2<9> r i out adc code (average of 8 consecutive measurements) 0x42 reg2 3 adc2<8> r i out adc code (average of 8 consecutive measurements) 0x42 reg2 2 adc2<7> r i out adc code (average of 8 consecutive measurements) 0x42 reg2 1 adc2<6> r i out adc code (average of 8 consecutive measurements) 0x42 reg2 0 adc2<5> r i out adc code (average of 8 consecutive measurements) 0x43 reg3 7 adc2<4> r i out adc code (average of 8 consecutive measurements) 0x43 reg3 6 adc2<3> r i out adc code (average of 8 consecutive measurements) 0x43 reg3 5 adc2<2> r i out adc code (average of 8 consecutive measurements) 0x43 reg3 4 adc2<1> r i out adc code (average of 8 consecutive measurements) 0x43 reg3 3 reserved r reserved 0x43 reg3 2 reserved. r reserved 0x43 reg3 1 reserved. r reserved 0x43 reg3 0 reserved. r reserved
5w, qi wireless power receiver with inte grated rectifier and ldo output 16 09/01/15 P9025AC datasheet table 8: read registers - frequency: where count is the decimal numb er represented by freq<10:1>. table 9: read registers ? miscellaneous functions byte address byte name bit field field name type default value description 0x44 reg4 7 freq<10> r frequency value (10 bits) 0x44 reg4 6 freq<9> r frequency value (10 bits) 0x44 reg4 5 freq<8> r frequency value (10 bits) 0x44 reg4 4 freq<7> r frequency value (10 bits) 0x44 reg4 3 freq<6> r frequency value (10 bits) 0x44 reg4 2 freq<5> r frequency value (10 bits) 0x44 reg4 1 freq<4> r frequency value (10 bits) 0x44 reg4 0 freq<3> r frequency value (10 bits) 0x45 reg5 7 freq<2> r frequency value (10 bits) 0x45 reg5 6 freq<1> r frequency value (10 bits) 0x45 reg5 5 reserved r reserved 0x45 reg5 4 reserved r reserved 0x45 reg5 3 reserved r reserved 0x45 reg5 2 reserved r reserved 0x45 reg5 1 reserved r reserved 0x45 reg5 0 reserved r reserved byte address byte name bit field field name type default value description 0x47 reg7 3 uvlo r 1: v rect is higher than uvlo threshold 0: no meaning. 0x47 reg7 2 clamp_on r 0: vrect is lower than ac clamp threshold 1: vrect is higher than ac clamp threshold 0x47 reg7 1 ldo_cl r 0: normal operation 1: ldo current limit exceeded. 0x47 reg7 0 reserved r reserved 0x48 reg8 7 charge_complete r 0: no meaning 1: charge complete 0x48 reg8 6 reserved r reserved 0x48 reg8 5 reserved r reserved 0x48 reg8 4 reserved r reserved 0x48 reg8 3 reserved r reserved 0x48 reg8 2 reserved r reserved 0x48 reg8 1 die_temp r 0: die temperature < 150c 1: die temperature >150c 0x48 reg8 0 tx_type r 0: tx is wpc 0x54 reg20 [7:0] wpc_id_b0 r unique ic identifier per wpc specification 0x55 reg21 [7:0] wpc_id_b1 r unique ic identifier per wpc specification f clk 65536 count --------------------- - =
09/01/15 17 5w, qi wireless power receiver wi th integrated rectifier and ldo output P9025AC datasheet table 10: read-write physical fod registers: 0x56 reg22 [7:0] wpc_id_b2 r unique ic identifier per wpc specification 0x57 reg23 [7:0] wpc_id_b3 r unique ic identifier per wpc specification 0x58 reg24 [7:0] wpc_id_b4 r unique ic identifier per wpc specification 0x59 reg25 [7:0] wpc_id_b5 r unique ic identifier per wpc specification 0x5a reg26 [7:0] wpc_id_b6 r unique ic identifier per wpc specification 0x5b reg27 [7:0] reserved r reserved 0x5c reg28 [7:0] reserved r reserved 0x5d reg29 [7:0] reserved r reserved 0x5e reg30 [7:0] reserved r reserved 0x5f reg31 [7:0] reserved r reserved 0x60 reg32 [7:0] reserved r reserved 0x61 reg33 [7:0] reserved r reserved 0x62 reg34 [7:0] reserved r reserved 0x63 reg35 [7:0] reserved r reserved 0x64 reg36 [7:0] reserved r reserved 0x65 reg37 [7:0] reserved r reserved byte address byte name bit field field name type default value description 0x49 reg9 0-7 fod9<0-7> r/w 0 mcf correction for region 1 io1, io2, io3 = 000 0x4a reg10 0-7 fod10<0-7> r/w 0 bcf correction for region 1 io1, io2, io3 = 000 0x4b reg11 0-7 fod11<0-7> r/w 0 mcf correction for region 2 io1, io2, io3 = 010 0x4c reg12 0-7 fod12<0-7> r/w 0 bcf correction for region 2 io1, io2, io3 = 010 0x4d reg13 0-7 fod13<0-7> r/w 0 mcf correction for region 3 io1, io2, io3 =100 0x4e reg14 0-7 fod14<0-7> r/w 0 bcf correction for region 3 io1, io2, io3 = 100 0x4f reg15 0-7 fod15<0-7> r/w 0 mcf correction for region 4 io1,io2,io3 = 110 0x50 reg16 0-7 fod16<0-7> r/w 0 bcf correction for region 4 io1, io2, io3 = 110 0x51 reg17 0-7 fod17<0-7> r/w 0 mcf correction for region 5 io1, io2, io3 = 111 0x52 reg18 0-7 fod18<0-7> r/w 0 bcf correction for region 5 io1, io2, io3 = 111 0x53 reg19 0-7 fod19<0-7> r/w 0 bcf correction for start-up phase byte address byte name bit field field name type default value description
5w, qi wireless power receiver with inte grated rectifier and ldo output 18 09/01/15 P9025AC datasheet package outline and package dimensions (nbg32) ? use epad option p1
09/01/15 19 5w, qi wireless power receiver wi th integrated rectifier and ldo output P9025AC datasheet package outline and package dimensions (nbg32), cont. u se epad 3.1mm sq.
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specifications d escribed herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2015 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support technical support request form ordering information note 1: custom configurations and a compact csp package is av ailable for qualified customers. contact your idt sales representa tive for more information note 2: factory-customized versions are available for qualified cu stomers. contact your idt sales representative for more infor mation. revision history part/order number marking package shipping packaging ambient temperature P9025AC-rnbgi P9025AC-rnbgi 5 x 5 x 0.75 mm 32-vfqfpn tray 0 to +85c P9025AC-rnbgi8 P9025AC-rnbgi 5 x 5 x 0.75 mm 32-vfqfpn tape and reel 0 to +85c date originator description of change 08/19/15 a.l. initial release. 09/01/15 a.l. 1. updated block diagram. 2. updated t j from ?0 to 150c? to ?0 to 125c?. 3. corrected minor textual typos.

▲Up To Search▲

Price & Availability of P9025AC

	To Download P9025AC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .